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🛡️ Fault Tolerant Matrix Computation on Systolic Arrays

Advanced FPGA implementation combining Algorithm-Based Fault Tolerance (ABFT) and Hamming Code error correction for reliable matrix computations in safety-critical applications. Published at IEEE ICCCNT 2025, IIT Indore.

Verilog HDL Xilinx Vivado FPGA ABFT Hamming Code IEEE Published

Verilog HDL Language

95% Fault Detection

IEEE 2025 Published

21 Files Verilog Code

Project Resources

21 HDL Files • 4 Modules

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Simulation Results

4 Images • FPGA Outputs

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System Diagrams

Block Diagrams • Schematics

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Project Overview

This project presents a novel approach to implementing fault-tolerant matrix multiplication using systolic arrays. The design incorporates both Algorithm-Based Fault Tolerance (ABFT) and Hamming Code error correction to detect and correct errors in real-time during matrix computations.

The system achieves 95% fault detection accuracy while maintaining computational efficiency, making it suitable for safety-critical applications in aerospace, medical devices, and autonomous systems.

Key Features

ABFT Integration

Algorithm-Based Fault Tolerance detects errors by verifying checksum rows and columns in real-time

Hamming Code

Provides error correction capability for single-bit errors with minimal overhead

Systolic Architecture

Parallel processing with efficient data flow for high-performance matrix operations

95% Detection Rate

Real-time error detection with 95% fault detection accuracy validated through FPGA simulation

FPGA Simulation Results

Hardware synthesis and simulation results from Xilinx Vivado platform

Simulation Output

Complete waveform analysis and timing diagram from testbench execution

Synthesis Results

Vivado synthesis run showing resource utilization and timing constraints

RTL Schematic

Register Transfer Level schematic view of the synthesized design

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